1. Field of the Invention
The present invention relates to a video signal output device and method, and more specifically to a video signal output device and method suitable for synchronous processing of video signals with a clock different from a clock on a transmission side.
2. Description of the Related Art
To transmit moving images in real time, for example, streaming-playback-based digital communications have been performed. In such digital communications, video signals are processed as follows.
An analog video signal input to a transmitter through broadcasting or the like is converted into digital video data with an analog/digital converter and stored in a transmission-side buffer. For efficient utilization of a network bandwidth, the digital video data is further encoded and compressed The digital video data or encoded information stored in the transmission-side buffer is packetized and transmitted to a receiver via a network.
The receiver receives the packets and stores digital video data in a reception-side buffer. The digital video data in the reception-side buffer is read at a predetermined timing in accordance with a clock and converted into analog video data with a digital/analog converter and then output and displayed as a moving image. If the digital video data is encoded and compressed, decoding processing is carried out to expand the video data to generate digital video data.
An IEEE1394-based high-speed serial bus has been employed as an interface suitable for such real-time transfer.
If data is transferred with an asynchronous transfer bus such as the IEEE1394-based bus, it is necessary to execute synchronous processing on data received by the receiver in accordance with an amount of data output from the transmitter.
In the case where the clocks differ between the transmission side and the reception side, if a clock rate on the transmission side is higher than that on the reception side, there is a possibility of the reception-side buffer overflowing. If the overflow occurs, video data is partially destructed on the reception side, resulting in a problem of unsmooth moving images.
In contrast, if a clock rate on the transmission side is lower than that on the reception side, there is a possibility of underflow occurring in the reception-side buffer. If the underflow occurs, video data cannot be displayed on the reception side, resulting in a problem of discontinuous moving images.
As a technique that overcomes these problems, Japanese Unexamined Patent Application Publication No. Hei 9-252292 discloses a method of monitoring data buffer occupancy on the reception side to control an oscillation frequency of a system clock on the transmission side to approximately synchronize the system clock on the transmission side and a system clock on the reception side. Further, Japanese Unexamined Patent Application Publication No. 2005-286749 discloses a method of monitoring an amount of received data stored in a reception-side buffer, and optionally adjusts a clock accuracy on the reception side if the stored data amount deviates from a reference data amount to thereby match a processing rate on the transmission side with that on the reception side.
As described above, as a countermeasure against the overflow or underflow of the reception-side buffer that receives video data, a buffer data amount is monitored to control an oscillation frequency of a clock on the reception side.
However, it is necessary to continuously monitor the buffer data amount to check an amount of data stored in the buffer in order to control a clock oscillation frequency, with the result that a device configuration is complicated. In general, a PLL (phase locked loop) is used to control an oscillation frequency. However, its configuration is complicated and costly.
Incidentally, the methods disclosed in Japanese Unexamined Patent Application Publication Nos. Hei 9-252292 and 2005-286749 do not employ a PLL. However, it is necessary to continuously monitor a buffer data amount to control a clock oscillation frequency, which puts a heavy burden on a CPU.